The Parts Built to Wear Out: A Conversation with Sahiti Nallagonda

Inside a plasma etch chamber, a wafer worth more than a car is exposed to corrosive gas, extreme heat, and a plasma environment where energetic ions and reactive chemical species remove material with nonometer-scale precision. Surrounding that wafer is a set of components engineered to absorb the damage on its behalf. They are called process kits and their job is to shape the plasma, protect critical chamber hardware and maintain process performance while withstanding gradual wear over time. The industry they support is now enormous. Global semiconductor sales are projected to reach $1.51 trillion in 2026, with memory alone climbing past $800 billion on the back of AI demand. Almost none of that output is possible without the unglamorous hardware sitting a few millimeters from the wafer edge, and when that hardware fails, the chips stop.

Sahiti Nallagonda has spent more than 10 years designing it. A senior mechanical engineer and inventor with 5 patents, she has served as the lead mechanical engineer and technical owner for process kit design, qualification, and sustaining programs across multiple etch platforms and product generations, working the boundary where materials science meets high-volume manufacturing. Her hardware is deployed in more than 1,000 chambers and is used daily by engineering, lab operations, service, and supplier teams across several organizations.

We spoke with Sahiti about why the parts nobody notices decide whether a fab hits its numbers, what happens when a component erodes in the wrong place, and how she designed hardware that replaced a decades-old approach to controlling the wafer edge.

Most people picture chipmaking as lithography and cleanrooms. What are they not seeing?

They are not seeing the consumables. Inside an etch chamber there is a set of parts surrounding the wafer, rings, liners, shields, and their entire job is to shape the process and take the abuse. The plasma is aggressive by design because it removes material with atomic-scale precision. But it does not politely stop at the wafer. It attacks everything it touches, including the hardware holding the wafer in place.

So those parts erode. That is expected and it is the point. What is not expected is for them to erode unevenly, or shed a particle, or shift by a fraction of a millimeter. Deviations as small as a few tens of hundreds of microns can alter local plasma conditions and affect wafer-edge performance. You end up with a die that fails at the perimeter of a wafer that cost thousands of dollars. A part that is technically a consumable turns out to be a yield-limiting component. Most people outside the industry have never heard of it. Everyone in the industry has an opinion about it.

You led process kit development across several platforms. What problem were you actually solving?

Several, and they compete with each other. Particle accumulation was one. Process byproducts builds up in the chamber over time, and if it accumulates in the wrong geometry it eventually flakes off and lands on a wafer. We addressed that with a wide-gap ring design that changed where deposits could collect and how they could be cleaned out. Erosion was another. A part made from a single material erodes at a single rate, which is fine until the erosion profile starts distorting the process. We moved to hybrid kits that combine quartz and silicon carbide, placing the more plasma resistant material in regions experiencing the highest ion and chemical loading.

Then there is the part I am proudest of. On some plasma etch architectures, wafer-edge behavior is influenced through capacitive coupling between chamber components. I worked on hardware that enabled direct electrical biasing of a process ring, providing additional control over wafer-edge conditions. I worked on hardware enabling pulsed voltage technology. It was first-of-a-kind hardware, and it gives process engineers real tunability at the wafer edge instead of a fixed condition they have to design around. That demonstrated how process-kit hardware can evolve from purely passive consumables into electrically integrated elements that contribute directly to process control.

Walk me through what makes this mechanically difficult.

Everything is fighting everything. The part has to survive high vacuum, Elevated temperatures and thermal gradients that can vary significantly across chamber components during manufacturing and maintenance cycles. It has to hold tolerance while it is doing that, because if it moves thermally in an unplanned direction, the gap changes and the process changes. It has to be installable by a technician in a fab at 2 a.m. without special tooling, and it has to go in the same way every time, because installation variability shows up as process variability. And now, with the wired ring, It has to maintain a stable electrical path across interfaces that are exposed to thermal cycling, contamination and plasma byproducts.

So the design space closes fast. Pick a material that survives the chemistry and it may not survive the thermal cycling. Solve for thermal and you may create a tolerance stack that no supplier can hold at volume. My job was rarely finding the clever solution. It was finding the solution that was still viable after you accounted for the supplier, the technician, the thermal budget, and 5 years of erosion. Most designs that look elegant on a screen die on one of those.

What went wrong that you did not see coming?

The failures that hurt are the ones that appear at scale, not in the lab. A kit qualifies beautifully on a test chamber, then goes into a fab and installation variability across sites produces results nobody can explain. Or a tolerance that was fine on the first article stacks badly against a mating part at volume. In a fab, that is expensive in a way people underestimate. Maintenance discipline drives overall equipment effectiveness directly, and a healthy fab wants a maintenance ratio of 4.0 or higher, meaning scheduled downtime should outweigh unscheduled downtime by at least 4 to 1. Every unplanned chamber event drags that ratio the wrong way.

That is where a lot of my work went, and it is the part that does not photograph well. Better fixture designs. Better calibration methods. Making installation repeatable so the same part behaves the same way in Taiwan and in Arizona. Across several programs, resolving mechanical, tolerance, and installation issues prevented roughly 50 chamber rework and field retrofit events. Each event can cost $50,000 to $70,000 in labor, parts, and lost lab time, and that is before you count the wafers that did not get processed. Nobody gives you an award for the failure that never happened. It is still the most valuable work I do.

You also review academic research in manufacturing. What do you look for in a paper?

Whether the authors have ever been in a fab. I peer review for the Journal of Intelligent Manufacturing, including a comparative study of heuristic and learning-based methods for anomaly detection in overhead hoist transportation systems, the automated tracks that move wafer carriers around a fab. It is a good example of the gap I look for. You can build a model that detects anomalies with impressive accuracy on a clean dataset. Whether it detects them early enough, and with few enough false alarms, that a fab would actually let it interrupt production is an entirely different question.

So I push on the constraints. What happens when the sensor drifts. What does a false positive cost the fab. Would anyone act on this output at 3 a.m. The strongest papers are honest that a method has limits, and they characterize those limits precisely. The weaker ones report an accuracy number and stop. Manufacturing is unforgiving in a way that a benchmark dataset is not, and reviewing keeps me sharp about the difference. It also keeps me current on approaches I might otherwise never encounter from inside a hardware group.

Hardware engineering has a reputation for being slow and incremental next to software. Fair?

Partly fair, and I think the framing is wrong. Hardware is slow because physics does not accept a patch. If a material erodes, you cannot push a fix over the air. You redesign, you re-qualify, you re-release, and the cycle takes months because it must. That is not conservatism, that is the cost of building something that has to hold up under conditions that would destroy almost anything else.

But incremental is the wrong word. Replacing capacitive coupling with a direct electrical connection at the wafer edge is not incremental. It changes what process engineers are allowed to do. The pace of hardware innovation is set by the qualification cycle, not by the ambition of the idea. What I would say to anyone dismissing this field is simple: every AI accelerator and every high-bandwidth memory die on the market passed through a chamber whose behavior was determined by a set of mechanical parts somebody had to design. The software runs on the hardware. The hardware runs on the parts.

Where does this work go next?

Toward more active hardware. Investment is running far ahead of where it was, with 300mm fab equipment spending rising 18% to $133 billion in 2026 and $151 billion in 2027, and the demands on the chamber are rising with it. Advanced transistor architectures and taller memory stacks need tighter edge control and less variation than the current generation of process kits can deliver. The passive part model, where a component just endures the plasma, is running out of headroom.

So the direction I am working toward is process kits that participate: electrically integrated, using new material combinations and contact strategies, tunable rather than fixed. The wired ring was a first step, not a destination. What I want, specifically, is for a process engineer to be able to adjust conditions at the wafer edge as deliberately as they adjust anything else in the chamber, instead of accepting whatever the hardware happens to impose. That is a mechanical design problem, and it is a long way from solved.